1. Field of the Invention
The present invention relates to an integrated semiconductor circuit, and more particularly, it relates to an integrated semiconductor circuit mounted on or incorporated in electronic equipment.
2. Description of Related Art
In the field of small electronic equipment such as mobile phones, many attempts have been made for size reduction, improvement in function, increase in density and high density packaging of electronic components incorporated in such small electronic equipment. Further, for size reduction of the electronic equipment itself, research aims to provide electronic equipment with components of as small number as possible. Following the trend, a plurality of integrated semiconductor circuits (hereinafter referred to as IC), which have been packed independently, are accommodated in a single package.
For example, Japanese Unexamined Patent Publication No. Hei 5 (1993)-21698 describes a semiconductor device wherein a discrete component is fixed via adhesive onto conductive plates arranged on a semiconductor chip such that the discrete component and the semiconductor chip are packed together in a single package. The structure of this semiconductor device is shown in a plan view of FIG. 9(a) and a section of FIG. 9(b) taken along the line D—D shown in FIG. 9(a).
This semiconductor device has the following construction. An insulating layer 82 is formed on a semiconductor chip 81, two conductive plates 83 and 84 are formed thereon, and a discrete component 85 is fixed thereon via a conductive adhesive 86. Electrodes are electrically connected to lead terminals 87 and the thus provided semiconductor assembly is packed in a resin encapsulate 88, thereby a semiconductor package which can be contact mounted to a substrate is manufactured.
FIGS. 10(a) and 10(b) show typically known small semiconductor device wherein a chip size package (CSP), i.e., a package having the same size as the semiconductor chip, is utilized. FIG. 10(b) is a section taken along the line E—E shown in FIG. 10(a).
The semiconductor device 91 shown in the FIGS. 10(a) and 10(b) has the following construction. A surface of a semiconductor chip 92 provided with a plurality of electrode pads 93 is covered with a first insulating layer 94 such that the electrode pads 93 are exposed and a plurality of wiring traces 95 are formed on the first insulating film 94, each of which being connected with the electrode pad 93 at one end and provided with an electrode pad 97 for mounting an external terminal at the other end. The wiring traces 95 are covered with a second insulating layer 96 such that the electrode pads 97 are exposed and external connection terminals 99 made of solder bumps are formed on the electrode pads 97.
However, the semiconductor device shown in FIGS. 9(a) and 9(b) involves difficulty in a process of adhering the insulating sheet 82 made of polyimide or the like which serves as an adhesive onto the semiconductor chip 81 to adhere thereto the conductive plates 83 and 84 made of Cu. That is, it is difficult to adhere a plate of 0.5×0.5 mm or smaller via the adhesive by mechanical movement, in particular to adhere a plurality of plates in a close positional relationship.
For mounting a discrete component of 0.5×0.8 mm used in the small electronic equipment, only two conductive portions are sufficient in a region of 0.7×1.0 mm. However, in FIG. 9, two conductive plates 83 and 84 occupy 70-80% of the area of the semiconductor chip 81. It seems that such a large size of them will allow easy handling of the conductive plates 83 and 84 and reduction of the length of the wire for connecting with a ground electrode or a power source electrode.